a. Field of the Invention
The present invention concerns addressing a static memory device. In particular, the present invention permits an address of a static random access memory device (or "SRAM") to be written to or read from using address and control signals for writing to or reading from a dynamic random access memory (or "DRAM").
b. Related Art
DRAMs are randomly addressable data storage devices. Storage locations in a DRAM are logically arranged in rows and columns. Accordingly, a storage location of a DRAM is addressed with a row address and a column address. More specifically, a row address is provided during a first time period ("a first cycle") and a column address is provided in a subsequent cycle. A row address strobe (or "RAS") signal indicates the presence of a valid row address on the address bus, while a column address strobe (or "CAS") signal indicates the presence of a valid column address on the address bus. Typically, CAS, RAS, and WE (write enable) signals applied to DRAMs are "active low". Thus, a falling edge of the RAS signal indicates that a valid row address exists on the address bus. Similarly, a falling edge of the CAS signal indicates that a valid column address exists on the address bus.
Many standard integrated circuit (or "I.C.") chips and customized I.C. chips are designed to read data from and write data to DRAMs and are configured to produce appropriate control signals such as a write enable (or "WE") signal, a RAS signal, a CAS signal, and appropriate row and column addresses to read from or write to an address of a DRAM. For example, Lucent Technologies sells a high level data link controller (or "HDLC") for controlling ISDN communications (part number T7901). This HDLC is designed to work with a DRAM. Unfortunately, DRAMs need refresh circuitry to maintain data stored in them. Such refresh circuitry adds to the cost of the DRAM. In some instances, the cost of a DRAM may be three (3) times the cost of an SRAM with comparable storage. Therefore, it would be desirable to permit chips (or other devices), designed to work with DRAMs, to instead work with SRAMs.